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FEATURES Fully Buffered Inputs and Outputs Fast Channel Switching: 10 ns High Speed > 750 MHz Bandwidth (-3 dB) 750 V/ s Slew Rate Fast Settling Time of 14 ns to 0.1% Low Power: 3.8 mA (AD8180), 6.8 mA (AD8182) Excellent Video Specifications (RL 1 k ) Gain Flatness of 0.1 dB Beyond 100 MHz 0.02% Differential Gain Error 0.02 Differential Phase Error Low Glitch: < 35 mV Low All-Hostile Crosstalk of -80 dB @ 5 MHz High "OFF" Isolation of -90 dB @ 5 MHz Low Cost Fast Output Disable Feature for Connecting Multiple Devices APPLICATIONS Pixel Switching for "Picture-In-Picture" Switching in LCD and Plasma Displays Video Switchers and Routers
750 MHz, 3.8 mA 10 ns Switching Multiplexers AD8180/AD8182*
FUNCTIONAL BLOCK DIAGRAM
IN0 1 GND 2 IN1 3 +VS 4 +1
DECODER
8 SELECT 7 ENABLE 6 OUT
+1
AD8180
5 -VS
IN0 A 1 GND 2 IN1 A 3 +VS 4 IN1 B 5 GND 6 IN0 B 7
+1
DECODER
14 SELECT A 13 ENABLE A 12 OUT A
+1
AD8182
+1
DECODER
11 -VS 10 OUT B 9 ENABLE B 8 SELECT B
+1
Table I. Truth Table PRODUCT DESCRIPTION
SELECT 0 1 0 1 ENABLE 0 0 1 1 OUTPUT IN0 IN1 High Z High Z
The AD8180 (single) and AD8182 (dual) are high speed 2-to-1 multiplexers. They offer -3 dB signal bandwidth greater than 750 MHz along with slew rate of 750 V/s. With better than 80 dB of crosstalk and isolation, they are useful in many high speed applications. The differential gain and differential phase error of 0.02% and 0.02, along with 0.1 dB flatness beyond 100 MHz make the AD8180 and AD8182 ideal for professional video multiplexing. They offer 10 ns switching time making them an excellent choice for pixel switching (picture-in-picture) while consuming less than 3.8 mA (per 2:1 mux) on 5 V supply voltages. Both devices offer a high speed disable feature allowing the output to be configured into a high impedance state. This allows multiple outputs to be connected together for cascading stages while the "OFF" channels do not load the output bus. They operate on voltage supplies of 5 V and are offered in 8and 14-lead plastic DIP and SOIC packages.
500mV /DIV
5ns/DIV
Figure 1. AD8180/AD8182 Switching Characteristics
*Protected under U.S. Patent Number 5,955,908.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD8180/AD8182-SPECIFICATIONS (@ T = +25 C, V =
A S
5 V, RL = 2 k
Min Typ
unless otherwise noted)
Max Units
AD8180A/AD8182A
Parameter SWITCHING CHARACTERISTICS Channel Switching Time1 50% Logic to 10% Output Settling 50% Logic to 90% Output Settling 50% Logic to 99.9% Output Settling ENABLE to Channel ON Time2 50% Logic to 90% Output Settling ENABLE to Channel OFF Time2 50% Logic to 90% Output Settling Channel Switching Transient (Glitch)3 DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Input Current Logic "0" Input Current DYNAMIC PERFORMANCE -3 dB Bandwidth (Small Signal)4 -3 dB Bandwidth (Small Signal)4 -3 dB Bandwidth (Large Signal) -3 dB Bandwidth (Large Si 0.1 dB Bandwidth4, 5 AD8180R AD8182R AD8180R AD8182R Conditions Channel-to-Channel IN0 = +1 V, IN1 = -1 V; RL = 1 k IN0 = +1 V, IN1 = -1 V; RL = 1 k IN0 = +1 V, IN1 = -1 V; RL = 1 k SEL = 0 or 1 IN0 = +1 V, -1 V or IN1 = -1 V, +1 V; RL = 1 k SEL = 0 or 1 IN0 = +1 V, -1 V or IN1 = -1 V, +1 V; RL = 1 k All Inputs Are Grounded, RL = 1 k SEL and ENABLE Inputs SEL and ENABLE Inputs SEL, ENABLE = +4 V SEL, ENABLE = +0.4 V VIN = 50 mV rms, RL = 5 k VIN = 50 mV rms, RL = 5 k VIN = 1 V rms, RL = 5 k VIN = 1 V rms, RL = 5 k VIN = 50 mV rms, RL = 5 k, RS = 0 VIN = 50 mV rms, RL = 1 k-5 k, RS = 150 VIN = 50 mV rms, RL = 1 k-5 k, RS = 125 2 V Step 2 V Step = 3.58 MHz, RL = 1 k = 3.58 MHz, RL = 1 k = 5 MHz, RL = 1 k = 30 MHz, RL = 1 k = 5 MHz, RL = 1 k = 30 MHz, RL = 1 k = 5 MHz, RL = 30 = 5 MHz, RL = 30 = 10 kHz-30 MHz C = 10 MHz, VO = 2 V p-p, RL = 1 k VIN = 1 V, RL = 2 k VIN = 1 V, RL = 10 k TMIN to T MAX Channel-to-Channel 2.0 10 2 750 640 120 110 930 780 150 135 100 210 210 750 14 0.02 0.02 -80 -65 -78 -63 -89 -93 4.5 -78 0.982 0.993 1 0.5 11 1 12 1 Channel Enabled (R Package) Channel Disabled (R Package) 2.2 1.5 1.5 3.3 3.1 30 27 10 1.7 6 57 51 3.8/6.8 1.3/2 4 -40 +85 4.5/8 4.75/8.5 2/3 2/3 0.04 0.04 0.8 200 3
5 10 14 10.5 11 25 / 35
ns ns ns ns ns mV V V nA A MHz MHz MHz MHz MHz MHz MHz V/s ns % Degrees dB dB dB dB dB dB nV/Hz dBc V/V V/V mV mV mV V/C A A nA/C M pF pF V V mA M pF V dB dB mA mA mA mA mA C
AD8180R 0.1 dB Bandwidth4, 5 AD8182R Slew Rate Settling Time to 0.1% DISTORTION/NOISE PERFORMANCE Differential Gain Differential Phase All Hostile Crosstalk6 AD8180R All Hostile Crosstalk6 OFF Isolation7 OFF Isolation7 Voltage Noise Total Harmonic Distortion DC/TRANSFER CHARACTERISTICS Voltage Gain8 Input Offset Voltage Input Offset Voltage Matching Input Offset Drift Input Bias Current Input Bias Current Drift INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Current Output Resistance Output Capacitance POWER SUPPLY Operating Range Power Supply Rejection Ratio Power Supply Rejection Ratio Quiescent Current AD8182R AD8180R AD8182R
0.986
12 15 4 5 7
TMIN to T MAX
RL = 500 9 Enabled Disabled Disabled (R Package)
3.0
1
+PSRR -PSRR
+VS = +4.5 V to +5.5 V, -VS = -5 V -VS = -4.5 V to -5.5 V, +V S = +5 V All Channels "ON" TMIN to T MAX All Channels "OFF" TMIN to T MAX AD8182, One Channel "ON"
4 54 45
OPERATING TEMPERATURE RANGE
-2-
REV. B
AD8180/AD8182
NOTES 1 ENABLE pin is grounded. IN0 = +1 V dc, IN1 = -1 V dc. SELECT input is driven with 0 V to +5 V pulse. Measure transition time from 50% of the SELECT input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (-1 V), or vice versa. 2 ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). State of SELECT input determines which channel is activated (i.e., if SELECT = Logic 0, IN0 is selected). Set IN0 = +1 V dc, IN1 = -1 V dc, and measure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, t OFF is the disable time, tON is the enable time. 3 All inputs are grounded. SELECT input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT pulse increases the glitch magnitude due to coupling via the ground plane. Removing the SELECT input termination will lower glitch, as does increasing R L. 4 Decreasing RL lowers the bandwidth slightly. Increasing C L lowers the bandwidth considerably (see Figure 19). 5 A resistor (RS ) placed in series with the mux inputs serves to optimize 0.1 dB flatness, but is not required. Increasing output capacitance will increase peaking and reduce bandwidth (see Figure 20.) 6 Select input which is not being driven (i.e., if SELECT is Logic 1, input activated is IN1); drive all other inputs with V IN = 0.707 V rms and monitor output at = 5 and 30 MHz. RL = 1 k (see Figure 13). 7 Mux is disabled (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with VIN = 0.446 V rms. Output is monitored at = 5 and 30 MHz. R L = 30 to simulate RON of one enabled mux within a system (see Figure 14). In this mode the output impedance is very high (typ 10 M ), and the signal couples across the package; the load impedance determines the crosstalk. 8 Voltage gain decreases for lower values of RL. The resistive divider formed by the mux enabled output resistance (27 ) and RL causes a gain which decreases as RL decreases (i.e., the voltage gain is approximately 0.97 V/V (3% gain error) for R L = 1 k). 9 Larger values of R L provide wider output voltage swings, as well as better gain accuracy. See Note 8. Specifications subject to change without notice.
MAXIMUM POWER DISSIPATION - Watts
ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Internal Power Dissipation2 AD8180 8-Lead Plastic DIP (N) . . . . . . . . . . . . . . . . 1.3 Watts AD8180 8-Lead Small Outline (R) . . . . . . . . . . . . . . 0.9 Watts AD8182 14-Lead Plastic DIP (N) . . . . . . . . . . . . . . . 1.6 Watts AD8182 14-Lead Small Outline (R) . . . . . . . . . . . . . 1.0 Watts Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . Observe Power Derating Curves Storage Temperature Range N and R Package . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP Package: JA = 90C/W; 8-Lead SOIC Package: JA = 155C/W; 14-Lead Plastic Package: JA = 75C/W; 14-Lead SOIC Package: JA = 120C/W, where P D = (T J-TA)/ JA.
While the AD8180 and AD8182 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves shown in Figures 2 and 3.
2.0 8-LEAD PLASTIC DIP PACKAGE TJ = +150 C 1.5
1.0
8-LEAD SOIC PACKAGE 0.5
ORDERING GUIDE
Model AD8180AN AD8180AR AD8180AR-REEL AD8180AR-REEL7 AD8182AN AD8182AR AD8182AR-REEL AD8182AR-REEL7 AD8180-EB AD8182-EB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Plastic DIP 8-Lead SOIC 13" Reel SOIC 7" Reel SOIC 14-Lead Plastic DIP 14-Lead Narrow SOIC 13" Reel SOIC 7" Reel SOIC Evaluation Board Evaluation Board Package Option N-8 SO-8 SO-8 SO-8 N-14 R-14 R-14 R-14
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
70 80 90
Figure 2. AD8180 Maximum Power Dissipation vs. Temperature
2.5 MAXIMUM POWER DISSIPATION - Watts TJ = +150 C 2.0 14-LEAD PLASTIC DIP PACKAGE
1.5
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8180 and AD8182 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure.
14-LEAD SOIC 1.0
0.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80 90
Figure 3. AD8182 Maximum Power Dissipation vs. Temperature
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8180/AD8182 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-3-
AD8180/AD8182-Typical Performance Curves
1 NORMALIZED OUTPUT - dB 0 -1 -2 -3 -4 -5 -6 -7 1M VIN = 50mV rms RL = 5k RS = 0 8180R
500mV /DIV
8182R
5ns/DIV
10M 100M FREQUENCY - Hz
1G
Figure 4. Channel Switching Characteristics
Figure 7. Small Signal Frequency Response
NORMALIZED FLATNESS - dB
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4
VIN = 50mV rms RL = 5k RS = 0
DUT OUT 250mV /DIV
8180R
8182R
10ns/DIV
1M
10M 100M FREQUENCY - Hz
1G
Figure 5. Enable and Disable Switching Characteristics
Figure 8. Gain Flatness vs. Frequency
3 0 INPUT/OUTPUT LEVEL - dBV -3 VIN = 0.5V rms -6 -9 VIN = 0.25V rms -12 -15 -18 -21 -24 25ns/DIV -27 1M VIN = 62.5mV rms VIN = 125mV rms RL = 1k VIN = 1.0V rms
50mV /DIV
10M 100M FREQUENCY - Hz
1G
Figure 6. Channel Switching Transient (Glitch)
Figure 9. Large Signal Frequency Response
-4-
REV. B
AD8180/AD8182
-10 -20 -30 CROSSTALK - dB -40
VIN 50 50 7 50 1 3 OUT A 1k
VIN = 0.707V rms RL = 1k
5
OUT B 1k
50mV /DIV
-50 -60 -70
AD8182
AD8182R -80 -90 AD8180R
-100 5ns/DIV -110 0.1M 1M 10M FREQUENCY - Hz 100M 1G
Figure 10. Small Signal Transient Response
Figure 13. All-Hostile Crosstalk vs. Frequency
-10 -20 -30 OFF ISOLATION - dB -40 -50
ALL INPUTS = 0.446V rms RL = 30
OUT A 30 50 VIN 50 OUT B 30
500mV /DIV
8180R OR 8182R ENABLE A = LOGIC 1 ENABLE B = LOGIC 0
-60 -70 -80 -90
AD8182
-100
8182R ENABLE A/B = LOGIC 1 1M 10M FREQUENCY - Hz 100M 1G
5ns/DIV
-110 0.03M 0.1M
Figure 11. Large Signal Transient Response
Figure 14. "OFF" Isolation vs. Frequency
100
0.020 0.015 0.010 0.005 0.000 -0.005 -0.010 -0.015 -0.020 1 DIFF PHASE - Degrees 2 3 4 5 IRE 0.02 0.01 0.00 -0.01 -0.02 1 2 3 4 5 IRE 6 7 8 9 10 11 6 7 DIFF GAIN - % RL = 1k NTSC
8
9
10
11
VOLTAGE NOISE - nV/ Hz
10
1
10
100
1k
10k 100k FREQUENCY - Hz
1M
10M 30M
Figure 12. Differential Gain and Phase Error
Figure 15. Voltage Noise vs. Frequency
REV. B
-5-
AD8180/AD8182-Typical Performance Curves
-25 -35 HARMONIC DISTORTION - dBc -45 -55 -65 -75 3RD HARMONIC NORMALIZED FLATNESS - dB +1 VOUT = 2V p-p RL = 1k VIN = 500mV rms RL = 5k CL = 100pF CL = 33pF CL = 10pF CL = 0pF 0 NORMALIZED OUTPUT - dB NORMALIZED OUTPUT - dB -1 -2 -3 -4 -5 -6 CL = 100pF -0.2 -0.3 -0.4 1M 4M 10M 40M 100M FREQUENCY - Hz 400M -7 -8 -9 1G
+0.1 0 -0.1
CL = 33pF
2ND HARMONIC
-85 -95 100k
1M
10M FREQUENCY - Hz
100M 200M 150M
Figure 16. Harmonic Distortion vs. Frequency
Figure 19. Frequency Response vs. Capacitive Load
31.6M DISABLED OUTPUT AND INPUT IMPEDANCE - ZOUT (DISABLED)
120
RS = 0 ENABLED OUTPUT IMPEDANCE - RS = 75 1.0 NORMALIZED FLATNESS - dB 0.8 0.6 0.4 0.2 RS = 75 0 -0.2 -0.4 1M RS = 150 4M 10M 40M 100M FREQUENCY - Hz 400M VIN = 50mV rms RL = 5k RS = 150 RS = 0
+1 0
3.16M
100
-1 -2 -3 -4 -5 -6 -7 -8 -9 1G
316k
ZIN (ENABLED)
80
31.6k
60
3.16k
ZOUT (ENABLED)
40
316
20
31.6 1k
10k
100k 1M 10M FREQUENCY - Hz
100M
0 1G
Figure 17. Disabled Output and Input Impedance vs. Frequency
Figure 20. Frequency Response vs. Input Series Resistance
0 -10 -20 PSRR - dB -30 -40 -50 -60 -70 0.03 OUTPUT VOLTAGE - Volts
5 4 3 2 1 0 -1 -2 -3 -4 -5 -5 -4 -3 -2 -1 0 1 2 INPUT VOLTAGE - Volts 3 4 5
+PSRR -PSRR
0.1
1 10 FREQUENCY - MHz
100
500
Figure 18. Power Supply Rejection vs. Frequency
Figure 21. Output Voltage vs. Input Voltage, RL = 1 k
-6-
REV. B
AD8180/AD8182
THEORY OF OPERATION
The AD8180 and AD8182 video multiplexers are designed for fast-switching (10 ns) and wide bandwidth (> 750 MHz). This performance is attained with low power dissipation (3.8 mA per active channel) through the use of proprietary circuit techniques and a dielectrically-isolated complementary bipolar process. These devices have a fast disable function that allows the outputs of several muxes to be wired in parallel to form a larger mux with little degradation in switching time. The low disabled output capacitance (1.7 pF) of these muxes helps to preserve the system bandwidth in larger matrices. Unlike earlier CMOS switches, the switched open-loop buffer architecture of the AD8180 and AD8182 provides a unidirectional signal path with minimal switching glitches and constant, low input capacitance. Since the input impedance of these muxes is nearly independent of the load impedance and the state of the mux, the frequency response of the ON channels in a large switch matrix is not affected by fanout. Figure 22 shows a block diagram and simplified schematic of the AD8180, which contains two switched buffers (S0 and S1) that share a common output. The decoder logic translates TTLcompatible logic inputs (SELECT and ENABLE) to internal, differential ECL levels for fast, low-glitch switching. The SELECT input determines which of the two buffers is enabled, unless the ENABLE input is HIGH, in which case both buffers are disabled and the output is switched to a high impedance state.
AD8180
I1 IN0 1 Q5 Q3 Q1 GND 2 S0 DECODER IN1 I2 Q6 Q4 Q2 +VS 4 I4 S1 Q8 5 -VS OUT I3 Q7 7 ENABLE 8 SELECT
for RL > 10 k. For heavier loads, the dc gain is approximately that of the voltage divider formed by the output impedance of the mux (typically 27 ) and RL. High speed disable clamp circuits at the bases of Q5-Q8 (not shown) allow the buffers to turn off quickly and cleanly without dissipating much power once off. Moreover, these clamps shunt displacement currents flowing through the junction capacitances of Q1-Q4 away from the bases of Q5-Q8 and to ac ground through low impedances. The two-pole high pass frequency response of the T switch formed by these clamps is a significant improvement over the one-pole high pass response of a simple series CMOS switch. As a result, board and package parasitics, especially stray capacitance between inputs and outputs may limit the achievable crosstalk and off isolation.
LAYOUT CONSIDERATIONS:
3
6
Figure 22. Block Diagram and Simplified Schematic of the AD8180 Multiplexer
Each open-loop buffer is implemented as a complementary emitter follower that provides high input impedance, symmetric slew rate and load drive, and high output-to-input isolation due to its 2 current gain. The selected buffer is biased ON by fast switched current sources that allow the buffer to turn on quickly. Dedicated flatness circuits, combined with the open-loop architecture of the AD8180 and AD8182, keep peaking low (typically < 1 dB) when driving high capacitive loads, without the need for external series resistors at the input or output. If better flatness response is desired, an input series resistance (RS) may be used (refer to Figure 20), although this will increase crosstalk. The dc gain of the AD8180 and AD8182 is almost independent of load
Realizing the high speed performance attainable with the AD8180 and AD8182 requires careful attention to board layout and component selection. Proper RF design techniques and low parasitic component selection are mandatory. Wire wrap boards, prototype boards, and sockets are not recommended because of their high parasitic inductance and capacitance. Instead, surface-mount components should be soldered directly to a printed circuit board (PCB). The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance ground path. The ground plane should be removed from the area near input and output pins to reduce stray capacitance. Chip capacitors should be used for supply bypassing. One end of the capacitor should be connected to the ground plane and the other within 1/4 inch of each power pin. An additional large (4.7 F-10 F) tantalum capacitor should be connected in parallel with each of the smaller capacitors for low impedance supply bypassing over a broad range of frequencies. Signal traces should be as short as possible. Stripline or microstrip techniques should be used for long signal traces (longer than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at the end using surface mount components. Careful layout is imperative to minimize crosstalk. Guards (ground or supply traces) must be run between all signal traces to limit direct capacitive coupling. Input and output signal lines should fan out away from the mux as much as possible. If multiple signal layers are available, a buried stripline structure having ground plane above, below, and between signal traces will have the best crosstalk performance. Return currents flowing through termination resistors can also increase crosstalk if these currents flow in sections of the finiteimpedance ground circuit that is shared between more than one input or output. Minimizing the inductance and resistance of the ground plane can reduce this effect, but further care should be taken in positioning the terminations. Terminating cables directly at the connectors will minimize the return current flowing on the board, but the signal trace between the connector and the mux will look like an open stub and will degrade the frequency response. Moving the termination resistors close to the input pins will improve the frequency response, but the terminations from neighboring inputs should not have a common ground return.
REV. B
-7-
AD8180/AD8182
APPLICATIONS Multiplexing two RGB Video Sources
A common video application requires two RGB sources to be multiplexed together before the selected signal is applied to a monitor. Typically one source would be the PC's normal output, the second source might be a specialized source such as MPEG video. Figure 23 shows how such a circuit could be realized using the AD8180 and AD8182 and three current feedback op amps. The video inputs to the multiplexers are terminated with 75 resistors. This has the effect of halving the signal amplitude of the applied signals. Because all three multiplexers are permanently active, the ENABLE pins are tied permanently low. The three SELECT pins are tied together and this signal is used to select the source. In order to drive a 75 back terminated load (RL = 150 ), the multiplexer outputs are buffered using the AD8001 current feedback op amp. A gain of two compensates for the signal halving by the AD8001 output back termination resistor so that the system has an overall gain of unity. If lower speed and crosstalk can be tolerated, either of the triple op amps, AD8013 or AD8073, can replace the three AD8001 op amps in the above circuit. Because both devices have bandwidths in the 100 MHz to 140 MHz range at a gain of +2, these amplifiers will dominate the frequency response of the circuit.
With no signal present, the total quiescent current of the circuit in Figure 23 is 25.6 mA (3.8 mA + 6.8 mA + 3 x 5 mA), or about 8.5 mA per channel. If either the AD8013 or AD8073 are used, the quiescent current will decrease to about 6.5 mA per channel. To reduce power consumption further, three AD8011 single op amps can be used. With a quiescent current of 1 mA, this will reduce the per channel quiescent current to about 4.5 mA.
Table II. Amplifier Options for RGB Multiplexer
Op Amp Comments AD8001 Highest Bandwidth, 440 MHz (G = +2), ISY = 5 mA AD8011 Lower Power Consumption, Bandwidth (G = +2) = 210 MHz, ISY = 1 mA AD8013 Triple Op Amp, Bandwidth (G = +2) = 140 MHz, ISY = 3.4 mA AD8073 Lower Power Triple Op Amp, Bandwidth (G = +2) = 100 MHz, ISY = 3.5 mA
681
681 +VS 10 F 0.1 F +
MPEG R G B 75 1 2 3 75 +VS 0.1 F + 75 10 F 1 2 0.1 F 75 +VS + 10 F 75 7 R G COMPUTER GRAPHICS B +1 8 3 4 5 6 +1
DECODER
75 AD8001 0.1 F +1
DECODER
8 7 6 5 0.1 F + 10 F -VS 681 +VS ENABLE -VS 681
10 F +
+1
4
AD8180
10 F 0.1 F 75 G MONITOR + R
+1
DECODER
14 13 12 ENABLE A 0.1 F 10 F 10 9 10 F -VS -VS ENABLE B 681 681 +VS 10 F 0.1 F RTERM AD8001 0.1 F 10 F SELECT -VS + + + 11 + AD8001 0.1 F
+1
B
AD8182
75
75
Figure 23. Multiplexing Two Component Video Sources
-8-
REV. B
AD8180/AD8182
Picture-in-Picture or Pixel Switching
CONTROL AND TIMING
Many high end display systems require simultaneous display of two video pictures (from two different sources) on one screen. Video conferencing is one such example. In this case the remote site might be displayed as the main picture with a picture of the local site "inset" for monitoring purposes. The circuit in Figure 23 could also be used to implement this "picture-in-picture" application. Implementing a picture-in-picture algorithm is difficult for several reasons. Both sources are being displayed simultaneously (i.e., during the same frame), both sources are in real time, and both must be synchronized. Figure 24 shows the raster scanning that takes place in all monitors. During every horizontal scan that includes part of the inset, the source must be switched twice (i.e., from main to inset and from inset to main). To avoid screen artifacts, it is critical that switching is clean and fast. The AD8180 and AD8182, in the above application, switch and settle to 0.1% accuracy in 14 ns. We quadratically add this value to the 10 ns settling time of the AD8001, and get an overall settling time of 17.2 ns. This yields a sharp, artifact-free border between the inset and the main video.
SEL B
C C D
R G B
CDS CDS
IN0 A OUT A IN1 A
SEL A
EN A EN B
AD8182
CDS REFERENCE IN1 B OUT B IN0 B
100
AD876 8/10-BIT 20MSPS A/D
4:1 MUX TRUTH TABLE SEL A, SEL B 0 0 1 1 ENA, ENB 0 1 0 1 OUTA, OUTB IN0A IN0B IN1A IN1B
Figure 25. Color Document Scanner
INSET VIDEO
The next step in the data acquisition process involves digitizing the three signal streams. Assuming that the analog to digital converter chosen has a fast enough sample rate, multiplexing the three streams into a single ADC is generally more economic than using one ADC per channel. In the example shown, we use the two 2-to-1 multiplexers in the AD8182 to create a 4-to-1 multiplexer. The enable control pins on the multiplexers allow the outputs to be wired directly together. Because of its high bandwidth, the AD8182 is capable of driving the switched capacitor input stage of the AD876 without additional buffering. In addition to having the required the bandwidth, it is necessary to consider the settling time of the multiplexer. In this case, the ADC has a sample rate of 20 MHz which corresponds to a sampling period of 50 ns. Typically, one phase of the sampling clock is used for conversion (i.e., all levels are held steady) and the other phase is used for switching and settling to the next channel. Assuming a 50% duty cycle, the signal chain must settle within 25 ns. With a settling time to 0.1% of 14 ns, the multiplexer easily satisfies this criterion. In the example shown, the fourth (spare) channel of the AD8182 is used to measure a reference voltage. This voltage would probably be measured less frequently than the R, G and B signals. Multiplexing a reference voltage offers the advantage that any temperature drift effects caused by the multiplexer will equally impact the reference voltage and the to-bemeasured signals. If the fourth channel is unused, it is good design practice to tie this input to ground.
MAIN VIDEO
MULTIPLEXER MUST SWITCH CLEANLY ON EACH CROSSING
Figure 24. "Picture-in-Picture," Pixel Switching
Color Document Scanner
Figure 25 shows a block diagram of a Color Document Scanner. Charge Coupled Devices (CCDs) find widespread use in scanner applications. A monochrome CCD delivers a serial stream of voltage levels, each level being proportional to the light shining on that cell. In the case of the color image scanner shown, there are three output streams, representing red, green and blue. Interlaced with the stream of voltage levels is a voltage representing the reset level (or black level) of each cell. A Correlated Double Sampler (CDS) subtracts these two voltages from each other in order to eliminate the relatively large offsets which are common with CCDs.
REV. B
-9-
AD8180/AD8182
EVALUATION BOARD
Evaluation boards for the AD8180R and AD8182R are available which have been carefully laid out and tested to demonstrate the specified high speed performance of the devices. Figure 26 and Figure 27 show the schematics of the AD8180 and AD8182 evaluation boards respectively. For ordering information, please refer to the Ordering Guide. Because the footprint of the AD8180 fits directly on to that of the AD8182, one board layout can be used for both devices. In the case of the AD8180, only the top half of the board is populated. Figure 28 shows the silkscreen of the component side and Figure 30 shows the silkscreen of the solder side. Figures 29 and 31 show the layout of the component side and solder side respectively.
The evaluation board is provided with 49.9 termination resistors on all inputs. This is to allow the performance to be evaluated at very high frequencies where 50 termination is most popular. To use the evaluation board in video applications, the termination resistors should be replaced with 75 resistors. The multiplexer outputs are loaded with 4.99 k resistors. In order to avoid large gain errors, these load resistors should be greater than or equal to 1 k. For connection to external instruments, oscilloscope scope probe adapters are provided. This allows direct connection of FET probes to the board. For verification of data sheet specifications, use of FET probes with a bandwidth > 1 GHz is recommended because of their low input capacitance. The probe adapters used on the board have the same footprint as SMA, SMB and SMC type connectors allowing easy replacement if necessary.
ENABLE R8 49.9
SELECT R9 49.9 IN0
R1 49.9 IN1 R10 49.9
1 2 3
+1
DECODER
8 7 6 5 C2 0.1 F + C3 10 F -VS OUT (SCOPE PROBE ADAPTER) R7 4.99k
+1
+VS C1 0.1 F + C4 10 F
4
AD8180R
UNLESS OTHERWISE NOTED, CONNECTORS ARE SMA TYPE
Figure 26. AD8180R Evaluation Board
ENABLE A R8 49.9 SELECT A IN0 A R1 49.9 IN1 A R10 49.9 C1 0.1 F +VS + C4 10 F R2 49.9 IN0 B R3 49.9 SELECT B R4 49.9 R5 49.9 UNLESS OTHERWISE NOTED, CONNECTORS ARE SMA TYPE 1 2 3 4 5 6 7 +1
DECODER
R9 49.9 OUTA (SCOPE PROBE ADAPTER) +1
DECODER
14 13 12 C2 0.1 F + C3 10 F R6 4.99k
R7 4.99k
+1
AD8182R
11 10 9 8
-VS
IN1 B
+1
OUTB (SCOPE PROBE ADAPTER)
ENABLE B
Figure 27. AD8182R Evaluation Board
-10-
REV. B
AD8180/AD8182
J1 IN0A ANALOG DEVICES AD8180/82 J10 J9 EVALUATION SEL A BOARD EN A R1 U1 R9 R8
J8
R7
J2 IN1A
A
R10 C1
V+
V-
C2 R2 J3 IN1B R3 R4 R5
J7
B
R6
C3
C4
IN0B J4
SEL B J5
EN B J6
Figure 28. Component Side Silkscreen
Figure 30. Solder Side Silkscreen
Figure 29. Board Layout (Component Side)
NOTES
Figure 31. Board Layout (Solder Side)
1. AD8180R/AD8182R Evaluation Board inputs are configured with 50 impedance striplines. This FR4 board type has the following stripline dimensions: 60-mil width, 12-mil gap between center conductor and outside ground plane "islands," and 62-mil board thickness. 2. Several types of SMA connectors can be mounted on this board: the side-mount type, which can be easily installed at the edges of the board, and the top-mount type, which is placed on top. When using the top-mount SMA connector, it is recommended that the stripline on the outside 1/8" of the board edge be removed with an X-Acto blade as this unused stripline acts as an open stub, which could degrade the smallsignal frequency response of the mux.
3. Input termination resistor placement on the evaluation board is critical to reducing crosstalk. Each termination resistor is oriented so that ground return currents flow counterclockwise to a ground plane "island." Although the direction of this ground current flow is arbitrary, it is important that no two input or output termination resistors share a connection to the same ground "island."
REV. B
-11-
AD8180/AD8182
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
14
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
8 7
1
4
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.210 (5.33) MAX
1
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX
PIN 1
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC
0.015 (0.381) 0.008 (0.204)
0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.100 0.070 (1.77) SEATING (2.54) 0.045 (1.15) PLANE BSC
0.015 (0.381) 0.008 (0.204)
8-Lead Plastic SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5
14-Lead SOIC (R-14)
0.3444 (8.75) 0.3367 (8.55)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80)
1
0.2440 (6.20) 4 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
PIN 1
0.0196 (0.50) x 45 0.0099 (0.25)
0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
0.0500 SEATING (1.27) PLANE BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
-12-
REV. B
PRINTED IN U.S.A.
C2182a-0-1/00 (rev. B)

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